I. Field of the Disclosure
The technology of the disclosure relates generally to processing of pipelined computer instructions in central processing unit (CPU)-based systems.
II. Background
The advent of “instruction pipelining” in modern computer architectures has yielded improved utilization of CPU resources and faster execution times of computer applications. Instruction pipelining is a processing technique whereby a throughput of computer instructions being processed by a CPU may be increased by splitting the processing of each instruction into a series of steps. The instructions are executed in a “processor pipeline” composed of multiple stages, with each stage carrying out one of the steps for each of a series of instructions. As a result, in each CPU clock cycle, steps for multiple instructions can be evaluated in parallel. A CPU may employ multiple processor pipelines to further boost performance.
Occasionally, a pipeline “hazard” may arise wherein an instruction is prevented from executing during its designated CPU clock cycle. For instance, a first instruction that generates data relied upon by a second instruction may not completely execute before the second instruction begins execution. In this instance, a hazard (specifically, a “read-after-write” hazard) may occur. To resolve the read-after-write hazard, the CPU may “stall” or delay execution of the second instruction until the first instruction has completely executed.
One particular instance in which the possibility of a read-after-write hazard may occur is during the execution of a masking instruction, which may include operations for reading a value from a register, applying a specified mask, and/or writing a resulting masked value back to the register. Such a masking instruction may be dependent upon the execution of a preceding write instruction, raising the possibility of encountering a read-after-write hazard.